(1) Field of the Invention
The present invention generally relates to bipolar transistors, and more particularly to improvements in a layer structure having a buried collector. Further, the present invention is concerned with a method of fabricating such a bipolar transistor.
(2) Description of the Prior Art
Most large-scale integrated circuits use silicon. Silicon bipolar transistors are known as high-speed transistors.
FIG. 1 is a cross-sectional view of a conventional silicon bipolar transistor. An n.sup.+ -type buried layer 52 is formed in a p-type silicon substrate 50. An n.sup.- -type silicon collector layer 54 is epitaxially grown on the n.sup.+ -type buried layer 52 and the p-type silicon substrate 50. Although not shown in FIG. 1, a p.sup.+ -type element isolation region is formed on the side of the n.sup.- -type collector layer 54, and hence the n.sup.- -type collector layer 54 is isolated from other transistors by a pn junction. A field oxide film 56 is selectively formed on the n.sup.- -type collector layer 54. Then, n-type impurities are added to the n.sup.- -type collector layer 54, which is separated from the other transistors by the field oxide film 56. Then, an n.sup.+ -type collector lead area 58 is formed so that it comes into contact with the n.sup.+ -type buried layer 52. During this process, n-type impurities are diffused into and thereby, to form, the n.sup.+ -type collector lead area 58.
Silicon is epitaxially grown on the entire surface, and thereby a p-type base region 60 and a base lead region 62 are formed at the same time as each other. The p-type base region 60 made of a p-type silicon single crystal is formed on the n.sup.- -type collector layer 54. The base lead region 62 made of polysilicon is formed on the field oxide film 56. Then, the base lead region 62 is patterned into a predetermined shape, and a silicon oxide film 64 is formed on the entire surface.
Thereafter, contact windows are formed in the silicon oxide film 64 formed on the p-type base region 60. One of the contact windows is then filled with an emitter lead electrode 66 formed with a polysilicon layer with n-type impurities added thereto. An n.sup.+ -type emitter region 68 is formed in a surface portion of the p-type base region 60 by a solid phase diffusion process in which impurities are derived from the emitter lead electrode 66. A base electrode 70 formed of aluminum is formed so that it is in contact with the base lead region 62 via the corresponding contact window. A collector electrode 72 formed of aluminum is formed so that it is in contact with the collector lead region 58 via the corresponding contact window.
In order to configure a circuit using bipolar transistors as described above, it is necessary to decrease parasitic capacitances coupled to nodes or terminals of the circuit. In the layer structure shown in FIG. 1, the n.sup.- -type collector layer 54 is isolated from the p.sup.+ -type element isolation region (not shown) by the pn junction, and a bottom surface portion of the n.sup.+ -type buried layer 52 is connected to the p-type silicon substrate by the pn junction. These pn junctions for isolation form large parasitic capacitors and prevent a high-speed operation of the circuit.
In order to overcome the above disadvantage and improve element isolation, it has been proposed that a thick oxide film formed by a LOCOS (Local Oxidation of Silicon) process or a U-shaped or V-shaped trench isolation be used instead of the pn-junction-based isolation. However, even with the above improvements, it is impossible to reduce to a negligible value the parasitic capacitance between the collector and the substrate, particularly at the bottom surface of the n.sup.+ -type buried layer 52 and the p-type silicon layer 50. Hence, a circuit based on the above-mentioned improvements does not operate at a high speed.